The present invention relates to the memory device, and more particularly to an address transition detection circuit generating pulses of a given width by detecting the transitions of the address signal being inputted.
The prior art in this circuit is shown in FIG. 1 through FIG. 3. As shown in FIG. 1, the prior circuit is composed of an inverter G1, a delay chain circuit 1, and an exclusive OR gate 1. As shown in FIG. 2 the circuit can obtain the address transition detection output(ATD) from the inputted address(Ai). In FIG. 3, in case that the address (Ai) makes a transition from high to low, the n channel MOSFETs(MN1,MN2) are turned ON, and then the current path is formed from the voltage source(Vcc) to the ground through the p channel transistor (MP1). In case that the address (Ai) makes a transition from low to high, the n channel MOSFETs (MN3,MN4) are turned ON, and then the current path is formed from the voltage source(Vcc) to the ground through the p channel MOSFET (MP1). Accordingly, this circuit had the problem for power loss because it had the ground node for performing logic operation.